Among the transistor structures favored for use in transistor structures with channel length of 50 nm or less, double gate (DG) or gate-all-around structures are widely considered as the most promising CMOS structures.
Different kinds of such multi-gate structures are envisioned, such as FinFET, vertical structures, or planar structures, according to the orientation of the conduction film and the respective fabrication process.
The planar architecture has the advantage to be able to stack several conduction channels vertically, i.e., to keep the same layout density as a bulk planar architecture, but to accommodate a higher current in comparison with the planar architecture. Inversely, it is also possible to reach the same current level in an integrated circuit with a much higher layout density.
FinFET devices have the disadvantage that they have a higher access resistance and a degraded NMOS mobility for (110) fin surfaces. Furthermore, problems arise in dopant implantation due to the shadowing effect. It has also proven difficult to reliably form fins with channel lengths below 20 nm.
US 2004/026290 A1 describes a process for fabricating a gate-all-around MOS transistor comprising one or several thin channels. The process disclosed in this document involves forming an insulating wall protruding from a substrate surface at a periphery of an active area of the silicon substrate. Subsequently, layer pairs are stacked.
Each pair comprises a silicon single-crystalline layer and a layer of a material, which is selectively etchable with respect to silicon. Subsequently, a strip of a material, which is selectively etchable with respect to silicon is formed above the previously deposited stack and the insulating walls, substantially above a central strip of the active area. The layer stack is then anisotropically etched on both sides of the strip and replaced by epitaxially grown silicon. A protection layer of a material different from that of this strip, the insulating walls end of the stack is then formed. After that, the strip is removed and the insulating walls, which are not protected by the protection layer are etched down the bottom of the layer stack.
Then, those layers, which are made of the material selectively etchable with respect to silicon are removed and a thin silicon oxide layer is formed at the surface of the silicon areas. Finally, the remaining cavity is filled with a conductive material that functions as the gate during operation of the transistor.
The process described in US 2007/026290 A1 is a single damascene approach. It is rather complex, which makes processing and the resulting devices expensive.
It would therefore be desirable to provide a more efficient fabrication process for a multi-gate FET.
It would also be desirable to provide a process that with only slight modifications can be used for the fabrication of a planar independent-gate FET or for the fabrication of a gate-all-around FET, or for a co-integration of single-gate FETs and planar independent-gate or gate-all-around FETs.